The present disclosure herein relates to semiconductor memory devices, and more particularly, to a synchronous semiconductor memory device having a delay locked loop and a method of controlling a delay locked loop block to save power.
Generally, a synchronous semiconductor memory device performs an operation of outputting data in synchronization with a clock being applied from the outside.
When a clock being applied from the outside is used inside the device, a time delay (a clock skew) caused by internal circuits inevitably occurs. A delay locked loop (DLL) circuit controls the time delay so that an internal clock may have the same phase as an external clock.
Since the application of a read latency operation and an on die termination (ODT) technology to a double data rate synchronous dynamic random access memory (DDR SDRAM) may require a synchronous operation of a clock, a DLL circuit may be mostly built in an SDRAM.
As an operation speed in a synchronous semiconductor memory device becomes high, an operation characteristic of a DLL circuit becomes more important. A measure for effectively reducing power being consumed in a DLL circuit may be needed to implement a low power operation.